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19-3286; Rev 0; 5/04
Low-Jitter 106.25MHz/212.5MHz Fibre-Channel Clock Generator
General Description
The MAX3610 is a low-jitter, high-performance, dual-rate clock generator optimized for 1Gbps/2Gbps/4Gbps Fibre-Channel applications. When connected with an external AT-cut crystal, the device generates a precision clock output by integrating a crystal oscillator with Maxim's low-noise phase-locked loop (PLL) providing a low-cost solution. By coupling Maxim's low-noise PLL design featuring a low-jitter generation VCO with an inexpensive fundamental mode crystal, the MAX3610 provides the optimum combination of low cost, flexibility, and high performance. The MAX3610 output frequency is selectable. When using a 26.5625MHz crystal, the output clock rate can be set to either 106.25MHz or 212.5MHz. When operating at 106.25MHz, the typical phase jitter is 0.7psRMS from 12kHz to 20MHz. The MAX3610A has low-voltage positive-emitter-coupled logic (LVPECL) clock output drivers. The MAX3610B has low-voltage differential-signal (LVDS) clock output drivers. The MAX3610 output drivers can also be disabled. The MAX3610 operates from a single +3.3V supply. The PECL version typically consumes 165mW, while the LVDS version typically consumes 174mW. Both devices are available in die form and have a 0C to +85C operating temperature range.
Features
Clock Output Frequencies: 106.25MHz or 212.5MHz Phase Jitter: 0.7psRMS LVPECL or LVDS Output Excellent Power-Supply Noise Rejection Supply Current: 50mA at +3.3V Supply (LVPECL) 53mA at +3.3V Supply (LVDS) 0C to +85C Temperature Range Optional Output Disable
MAX3610
Ordering Information
PART MAX3610AU/D MAX3610BU/D TEMP RANGE 0C to +85C 0C to +85C PINPACKAGE Die Die OUTPUTS LVPECL LVDS
Applications
Fibre-Channel Hard Disk Drives Host Bus Adapters Raid Controllers Fibre-Channel Switches
Dice are designed to operate from 0C to +85C, but are tested and guaranteed only at TA = +25C.
Typical Operating Circuits
+3.3V +3.3V
0.1F
0.1F
OE AT CUT CRYSTAL X1
VCC
FREQSET
+3.3V AT CUT CRYSTAL
OE
VCC
FREQSET
+3.3V
MAX3610A
OUT+ DEVICE WITH LVPECL INPUTS
X1
MAX3610B
OUT+ 100 DEVICE WITH LVDS INPUTS
X2 GND
OUT50 50
X2 GND
OUT-
OPERATING AT 106.25MHz LVPECL OUTPUTS VCC -2V OPERATING AT 106.25MHz LVDS OUTPUTS
________________________________________________________________ Maxim Integrated Products
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For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Low-Jitter 106.25MHz/212.5MHz Fibre-Channel Clock Generator MAX3610
ABSOLUTE MAXIMUM RATINGS
Supply Voltage ......................................................-0.5V to +5.0V Voltage at FREQSET, OE............................-0.5V to (VCC + 0.5V) Voltage at X1 .........................................................-0.5V to +0.8V Voltage at X2 .....................................................................0 to 2V PECL Output Current ..........................................................56mA LVDS Output Voltage .................................-0.5V to (VCC + 0.5V) Operating Temperature Range...............................0C to +85C Storage Temperature Range .............................-65C to +160C Processing Temperature..................................................+400C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, TA = 0C to +85C. Typical values are at VCC = +3.3V and TA = +25C, unless otherwise noted.) (Note 1 )
PARAMETER Supply Current SYMBOL ICC (Note 2) CONDITIONS LVPECL LVDS VCC 1.025 VCC 1.81 MIN TYP 50 53 MAX 65 67 VCC 0.88 VCC 1.62 1.475 0.925 250 400 25 UNITS mA
LVPECL OUTPUT SPECIFICATIONS (Note 3) Output High Voltage Output Low Voltage VOH VOL 0C to +85C 0C to +85C V V
LVDS OUTPUT SPECIFICATIONS (Figure 1) LVDS Output High Voltage LVDS Output Low Voltage LVDS Differential Output Voltage LVDS Change in Magnitude of Differential Output for Complementary States LVDS Offset Output Voltage (Output Common-Mode Voltage) LVDS Change in Magnitude of Output Offset Voltage for Complementary States LVDS Differential Output Impedance LVDS Output Current TTL Control Input-Voltage High TTL Control Input-Voltage Low Input Current (Input High) Input Current (Input Low) CLOCK OUTPUT SPECIFICATIONS Clock Output Frequency Crystal Oscillation Circuit Input Capacitance FREQSET = TTL High, VCC, or NC FREQSET = TTL Low or GND 106.25 212.5 12 MHz pF VIH VIL IIH IIL -10 -50 Outputs shorted together 2 0.8 +10 +10 CONTROL INPUT SPECIFICATIONS (FREQSET, OE) V V A A VOH VOL |VOD| |VOD| V V mV mV
VOS |VOS|
1.125
1.275
V
25
mV mA
80
100
140 12
2
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Low-Jitter 106.25MHz/212.5MHz Fibre-Channel Clock Generator
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0V to +3.6V, TA = 0C to +85C. Typical values are at VCC = +3.3V and TA = +25C, unless otherwise noted.) (Note 1 )
PARAMETER Phase Jitter Accumulated Deterministic Jitter Due to Reference Spurs 10kHz Accumulated Deterministic Jitter Due to Power-Supply Noise (Note 4) 100kHz 200kHz 1MHz Clock-Output Edge Speeds Clock-Output Duty Cycle Oscillation Startup Time (Note 5) 100Hz 1kHz Clock-Output SSB Phase Noise Measured at 106.25MHz 10kHz 100kHz 1MHz 10MHz -90 -112 -115 -123 -142 -147 dBc/Hz t R , tF 20% to 80% LVPECL outputs LVDS outputs 250 200 49 SYMBOL PJRMS CONDITIONS 12kHz to 20MHz MIN TYP 0.7 3.0 3.0 27 15 7 600 600 51 5 ps % ms 69 43 psP-P MAX 1.0 UNITS psRMS psP-P
MAX3610
Note 1: AC parameters are guaranteed by design and characterization. Note 2: Outputs are enabled and unloaded. Note 3: When LVPECL output is disabled to high impedance, the typical output off-current is <100A for nominal LVPECL signal levels at the output. Note 4: Measured with 50mVP-P sinusoidal signal on the supply, from 10kHz to 1MHz. Note 5: Including oscillator startup time and PLL acquisition time, measured after VCC reaches 3.0V from power on.
OUT+ D OUTVOUT+ SINGLE-ENDED OUTPUT VOUT|VOD| VOH VOS VOL RL = 100 V VOD
+VOD DIFFERENTIAL OUTPUT 0V (DIFF) 0V -VOD VODP-P = VOUT+ - VOUT-
Figure 1. LVDS Swing Definitions
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Low-Jitter 106.25MHz/212.5MHz Fibre-Channel Clock Generator MAX3610
Typical Operating Characteristics
(VCC = 3.3V, TA = +25C, unless otherwise noted.)
POWER-SUPPLY CURRENT vs. TEMPERATURE
MAX3610 toc01
OUTPUT DETERMINISTIC JITTER DUE TO POWER-SUPPLY NOISE vs. FREQUENCY
MAX3610 toc02
OUTPUT DETERMINISTIC JITTER DUE TO POWER-SUPPLY NOISE vs. SUPPLY VOLTAGE
OUTPUT DETERMINISTIC JITTER (psP-P) 45 40 35 30 25 20 15 10 5 0 3.0 200kHz SUPPLY NOISE 3.1 3.2 3.3 3.4 3.5 3.6 100kHz SUPPLY NOISE 212.5MHz CLOCK OUTPUT 50mVP-P SUPPLY NOISE VOLTAGE AMPLITUDE
MAX3610 toc03
80 75 SUPPLY CURRENT (mA) 70 65 60 55 50 LVPECL DEVICE 45 40 0 10 20 30 40 50 60 70 80 SUPPLY VOLTAGE (V) LVDS DEVICE
80 OUTPUT DETERMINISTIC JITTER (psP-P) 70 60 50 40 30 20 10 0 1 10 100 100mVP-P NOISE 50mVP-P NOISE
50
1000
FREQUENCY OF POWER-SUPPLY NOISE VOLTAGE (kHz)
SUPPLY VOLTAGE LEVEL (V)
Pin Description
PAD 1, 2, 3, 6, 7, 9, 10, 11, 15-18 4 5 8 12 13 14 19 20 NAME N.C. X1 X2 OE OUTGND OUT+ FREQSET VCC No Connection Crystal Oscillator Input Crystal Oscillator Output Output Enable. On-chip pullup resistor. Connect OE to logic-high, VCC, or leave open to enable the output clock. Connect OE to logic-low or GND to disable the output clock. LVPECL output clock is set to high impedance when disabled. LVDS output clock is latched to a differential high when disabled. Negative Clock Output, LVPECL or LVDS Ground Positive Clock Output, LVPECL or LVDS Output Frequency Select. On-chip pullup resistor. Connect FREQSET to logic-high, VCC, or leave open to set the output clock rate to 106.25MHz. Connect FREQSET to logic-low or GND to set the output clock rate to 212.5MHz. +3.3V Supply FUNCTION
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Low-Jitter 106.25MHz/212.5MHz Fibre-Channel Clock Generator MAX3610
Functional Diagram
FREQSET
MAX3610A MAX3610B
X1 OSCILLATOR GAIN CIRCUIT X2 PFD LOOP FILTER VCO COUNTER M OUTPUT BUFFER OUT+ OUT-
PLL
COUNTER N OE
Figure 2. Functional Diagram
Detailed Description
The MAX3610 contains all of the blocks needed to form a precision Fibre-Channel clock except for the external crystal, which must be supplied separately. Figure 2 shows a functional block diagram of the MAX3610. The MAX3610 consists of a crystal oscillator, a low-noise PLL, selectable clock-divider circuitry, and an output buffer. Optimal performance is achieved by integrating the crystal oscillator with a low-noise PLL. The PLL consists of a digital phase/frequency detector (PFD) and low-jitter generation VCO. The VCO signal is scaled by clockdivider circuitry and applied to the output buffer. The MAX3610 is available with either LVPECL or LVDS output buffers (see the Ordering Information).
scaling the VCO output frequency. Clock-divider circuit N applies a scaled version of the output clock signal to the PFD. A TTL low applied to FREQSET, sets clockdivider M ratio to 16, and clock-divider N ratio to 8. With FREQSET pulled low, the output clock rate is 212.5MHz. A TTL high applied to FREQSET sets the clock-divider M ratio to 32, and clock-divider N ratio to 4. With FREQSET pulled high, the output clock rate is 106.25MHz.
Output Drivers
The MAX3610 is available with either LVPECL (MAX3610A) or LVDS (MAX3610B) output buffers. When not needed, the output buffers can be disabled. When disabled, the LVPECL output buffer goes to a high-impedance state. However, the LVDS outputs go to a differential 1 (OUT+ latched high and OUT- latched low) when the outputs are disabled.
Oscillator Gain Circuit
The input capacitance of the oscillator gain circuit is trimmed to 12pF of capacitance and produces oscillations at 26.5625MHz when interfaced with the appropriate external crystal (see Table 1 for the external crystal specifications).
Design Procedure
Crystal Resonator Specifications
The MAX3610 is designed to operate with an inexpensive fundamental mode crystal. Table 1 specifies the characteristics of a typical crystal to be interfaced with the MAX3610.
PLL
The PLL generates a 1.7GHz high-speed clock signal based on the 26.5625MHz crystal oscillator output. Clock-divider circuit M generates the output clock by
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Low-Jitter 106.25MHz/212.5MHz Fibre-Channel Clock Generator MAX3610
Table 1. Crystal Resonator Specifications
PARAMETER Crystal Nominal Oscillator Frequency Shunt Capacitance (Co) Co/Cs Load Capacitance (Note 6) Equivalent Series Resistance (ESR) Maximum Crystal Drive Level VALUE Fundamental AT-cut 26.5625MHz 2pF 280 12pF 5 to 40 500W
X1 CS RS LS X2 CO
Figure 3. Equivalent Crystal Resonator Circuit Model
Note 6: The load capacitance includes the oscillation-circuit input capacitance, as well as the parasitic capacitance caused from the assembling/packaging of the blank crystal and IC.
Applications Information
VCC VCC
OUT+
ESD STRUCTURES
OUT+
OUT-
OUT-
ESD STRUCTURES
Figure 4. LVPECL Output Stage
Figure 5. LVDS Output Stage
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Low-Jitter 106.25MHz/212.5MHz Fibre-Channel Clock Generator
Table 2. Bond Pad Coordinates
PAD BP1 BP2 BP3 BP4 BP5 BP6 BP7 BP8 *BP9 BP10 BP11 BP12 BP13 BP14 BP15 BP16 BP17 BP18 BP19 BP20 NAME N.C. N.C. N.C. X1 X2 N.C. N.C. OE N.C. N.C. N.C. OUTGND OUT+ N.C. N.C. N.C. N.C. FREQSET VCC COORDINATES X (m) 36.1 13.7 13.7 17.9 16.5 16.5 16.5 15.1 16.5 167.7 1119.7 1613.9 1613.9 1613.9 1612.5 1611.1 577.9 435.1 306.3 169.1 Y (m) 1362.4 1193 1060 742.2 613.4 474.8 344.6 210.2 39.4 33.8 36.6 50.6 187.8 325 613.4 753.4 1366.6 1369.4 1369.4 1366.6
MAX3610
Pad Information
Bond pad coordinates specify center pad location. All bond pad coordinates are referenced to the lower most left corner of the index pad (see Application Note HFAN 9.0).
*Index pad
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Low-Jitter 106.25MHz/212.5MHz Fibre-Channel Clock Generator MAX3610
Chip Topography
TRANSISTOR COUNT: 2920 SUBST ELECTRICALLY ISOLATED PROCESS: SiGe BIPOLAR DIE SIZE: 1.88mm x 1.63mm
Package Information
For the latest package outline information, go to www.maxim-ic.com/packages.
VCC
FREQSET
N.C.
N.C.
N.C.
1
20
19
18
17
N.C.
2
N.C.
3
X1
4
16
N.C. 0.064" 1.63mm
X2
5
15
N.C.
N.C.
6
N.C.
7
14
OUT+
OE
8
13
GND
N.C.
9
10
11
12
N.C. 0.074" 1.88mm
N.C.
OUT-
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
8 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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